View SN65MLVD201B_9069977.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. sn65mlvd206b sllsex9 ? december 2016 sn65mlvd206b multipoint-lvds line drivers and receivers (transceivers) with iec esd protection 1 1 features 1 ? compatible with the m-lvds standard tia/eia- 899 for multipoint data interchange ? low-voltage differential 30- ? to 55- ? line drivers and receivers for signaling rates (1) up to 200 mbps, clock frequencies up to 100 mhz ? type-1 receiver incorporates 25 mv of hysteresis (201b and 203b) ? type-2 receiver provides an offset threshold to detect open-circuit and idle-bus conditions (206b and 207b) ? bus i/o protection ? > 8-kv hbm ? > 8-kv iec 61000-4-2 contact discharge ? controlled driver output voltage transition times for improved signal quality ? -1-v to 3.4-v common-mode voltage range allows data transfer with 2 v of ground noise ? bus pins high impedance when disabled or v cc 1.5 v ? 100-mbps devices available (sn65mlvd200b, 202b, 204b, 205b) ? improved alternatives to sn65mlvd201, 203, 206, and 207 (1) the signaling rate of a line is the number of voltage transitions that are made per second expressed in the bps of the unit (bits per second). 2 applications ? low-power, high-speed, and short-reach alternative to tia/eia-485 ? backplane or cabled multipoint data and clock transmission ? cellular base stations ? central office switches ? network switches and routers 3 description the SN65MLVD201B, sn65mlvd203b, sn65mlvd206b, sn65mlvd207b devices are multipoint-low-voltage differential (m-lvds) line drivers and receivers which are optimized to operate at signaling rates up to 200 mbps. this device family has robust 3.3-v drivers and receivers in the standard soic footprint for demanding industrial applications. the bus pins are robust to esd events, with high levels of protection to human-body model and iec contact discharge specifications. these devices each combine a differential driver and a differential receiver (transceiver), which operate from a single 3.3-v supply. the transceivers are optimized to operate at signaling rates up to 200 mbps. the sn65mlvd20xb have enhancements over similar devices. improved features include a controlled slew rate on the driver output to help minimize reflections from unterminated stubs, resulting in better signal integrity. the same footprint definition was maintained, allowing for an easy drop- in replacement for a system performance upgrade. the devices are characterized for operation from ? 40 c to 85 c. the sn65mlvd20xb m-lvds transceivers are part of ti ? s extensive m-lvds portfolio . device information (1) part number package body size (nom) SN65MLVD201B soic (8) 4.90 mm 3.91 mm sn65mlvd206b sn65mlvd203b soic (14) 8.65 mm 3.91 mm sn65mlvd207b (1) for all available packages, see the orderable addendum at the end of the datasheet. spacer simplified schematic SN65MLVD201B, sn65mlvd206b simplified schematic sn65mlvd203b, sn65mlvd207b 54 2 3 de d re r 12 11 ab 10 9 yz copyright ? 2016, texas instruments incorporated 4 31 2 de d re r 67 ab copyright ? 2016, texas instruments incorporated productfolder sample &buy technical documents tools & software support &community
2 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated table of contents 1 features .................................................................. 1 2 applications ........................................................... 1 3 description ............................................................. 1 4 revision history ..................................................... 2 5 pin configuration and functions ......................... 3 6 specifications ......................................................... 4 6.1 absolute maximum ratings ...................................... 4 6.2 esd ratings .............................................................. 4 6.3 recommended operating conditions ....................... 4 6.4 thermal information .................................................. 4 6.5 electrical characteristics ........................................... 5 6.6 electrical characteristics ? driver ............................. 5 6.7 electrical characteristics ? receiver ........................ 6 6.8 electrical characteristics ? bus input and output ... 6 6.9 switching characteristics ? driver ............................ 7 6.10 switching characteristics ? receiver ...................... 7 6.11 typical characteristics ............................................ 8 7 parameter measurement information .................. 8 8 detailed description ............................................ 16 8.1 overview ................................................................. 16 8.2 functional block diagrams ..................................... 16 8.3 feature description ................................................. 16 8.4 device functional modes ........................................ 17 9 application and implementation ........................ 19 9.1 application information ............................................ 19 9.2 typical application ................................................. 19 10 power supply recommendations ..................... 24 11 layout ................................................................... 24 11.1 layout guidelines ................................................. 24 11.2 layout example .................................................... 27 12 device and documentation support ................. 29 12.1 documentation support ....................................... 29 12.2 receiving notification of documentation updates 29 12.3 community resources .......................................... 29 12.4 trademarks ........................................................... 29 12.5 electrostatic discharge caution ............................ 29 12.6 glossary ................................................................ 29 13 mechanical, packaging, and orderable information ........................................................... 29 4 revision history date revision notes december 2016 * initial release.
3 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated 5 pin configuration and functions d package 8-pin soic top view d package 14-pin soic top view pin functions pin type description name d8 no. d14 no. a 6 12 i/o differential i/o b 7 11 i/o differential i/o d 4 5 input driver input de 3 4 input driver enable pin; high = enable, low = disable gnd 5 6, 7 power supply ground nc ? 1, 8 nc no internal connection r 1 2 output receiver output re 2 3 input receiver enable pin; high = disable, low = enable v cc 8 13, 14 power power supply, 3.3 v y ? 9 i/o differential i/o z ? 10 i/o differential i/o 1 nc 14 vcc 2 r 13 vcc 3 re 12 a 4 de 11 b 5 d 10 z 6 gnd 9 y 7 gnd 8 nc not to scale 1 r 8 vcc 2 re 7 b 3 de 6 a 4 d 5 gnd not to scale
4 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions . exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values, except differential i/o bus voltages, are with respect to network ground terminal. 6 specifications 6.1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) (1) min max unit supply voltage range, v cc (2) ? 0.5 4 v input voltage range d, de, re ? 0.5 4 v a, b (201b, 206b) ? 1.8 4 v a, b (203b, 207b) ? 4 6 output voltage range r ? 0.3 4 v a, b, y or z ? 1.8 4 v continuous power dissipation see the thermal information table storage temperature, t stg ? 65 150 c 6.2 esd ratings value unit v (esd) electrostatic discharge contact discharge, per iec 61000-4-2 a, b, y and z 8000 v human body model (hbm), per ansi/esda/jedec js-001, all pins a, b, y and z 8000 all pins except a, b, y and z 4000 charged device model (cdm), per jedec specification jesd22-c101, all pins all pins 1500 6.3 recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v cc supply voltage 3 3.3 3.6 v v ih high-level input voltage 2 v cc v v il low-level input voltage gnd 0.8 v voltage at any bus terminal v a , v b , v y or v z ? 1.4 3.8 v |v id | magnitude of differential input voltage v cc v r l differential load resistance 30 50 ? 1/t ui signaling rate 200 mbps t a operating free-air temperature ? 40 85 c (1) for more information about traditional and new thermal metrics, see the semiconductor and ic package thermal metrics application report. 6.4 thermal information thermal metric (1) SN65MLVD201B sn65mlvd206b sn65mlvd203b sn65mlvd207b unit d (soic) d (soic) 8 pins 14 pins r ja junction-to-ambient thermal resistance 112.2 87.4 c/w r jc(top) junction-to-case (top) thermal resistance 56.7 46.6 r jb junction-to-board thermal resistance 52.8 42 jt junction-to-top characterization parameter 10.3 11.3 jb junction-to-board characterization parameter 52.3 71.7
5 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated (1) all typical values are at 25 c and with a 3.3-v supply voltage. 6.5 electrical characteristics over recommended operating conditions (unless otherwise noted) (1) parameter test conditions min typ max unit i cc supply current driver only re and de at v cc , r l = 50 ? , all others open 13 22 ma both disabled re at v cc , de at 0 v, r l = no load, all others open 1 4 both enabled re at 0 v, de at v cc , r l = 50 ? , all others open 16 24 receiver only re at 0 v, de at 0 v, all others open 4 13 p d device power dissipation r l = 50 ? , input to d is a 50-mhz 50% duty cycle square wave, de = high, re = low, t a = 85 c 100 mw (1) the algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet. (2) all typical values are at 25 c and with a 3.3-v supply voltage. (3) measurement equipment accuracy is 10 mv at ? 40 c (4) hp4194a impedance analyzer (or equivalent) 6.6 electrical characteristics ? driver over recommended operating conditions unless otherwise noted parameter test conditions min (1) typ (2) max unit |v ab | or |v yz | differential output voltage magnitude (3) see figure 3 480 650 mv |v ab | or |v yz | change in differential output voltage magnitude between logic states ? 50 50 mv v os(ss) steady-state common-mode output voltage see figure 4 0.8 1.2 v v os(ss) change in steady-state common-mode output voltage between logic states ? 50 50 mv v os(pp) peak-to-peak common-mode output voltage 150 mv v y(oc) or v a(oc) maximum steady-state open-circuit output voltage see figure 8 0 2.4 v v z(oc) or v b(oc) maximum steady-state open-circuit output voltage 0 2.4 v v p(h) voltage overshoot, low-to-high level output see figure 6 1.2 v ss v v p(l) voltage overshoot, high-to-low level output ? 0.2 v ss v i ih high-level input current (d, de) v ih = 2 v to v cc 0 10 a i il low-level input current (d, de) v il = gnd to 0.8 v 0 10 a |i os | differential short-circuit output current magnitude see figure 5 24 ma i oz high-impedance state output current (driver only) ? 1.4 v (v y or v z ) 3.8 v, other output = 1.2 v ? 15 10 a i o(off) power-off output current ? 1.4 v (v y or v z ) 3.8 v, other output = 1.2 v, 0 v v cc 1.5 v ? 10 10 a c y or c z output capacitance v i = 0.4 sin(30e6 t) + 0.5 v, (4) other input at 1.2 v, driver disabled 3 pf c yz differential output capacitance v ab = 0.4 sin(30e6 t) v, (4) driver disabled 2.5 pf c y/z output capacitance balance, (c y /c z ) 0.99 1.01 pf
6 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated (1) all typical values are at 25 c and with a 3.3-v supply voltage. (2) measurement equipment accuracy is 10 mv at ? 40 c (3) hp4194a impedance analyzer (or equivalent) 6.7 electrical characteristics ? receiver over recommended operating conditions unless otherwise noted parameter test conditions min typ (1) max unit v it+ positive-going differential input voltage threshold (2) type 1 see figure 10 , table 1 , and table 2 50 mv type 2 150 v it- negative-going differential input voltage threshold (2) type 1 ? 50 mv type 2 50 v hys differential input voltage hysteresis, (v it+ ? v it ? ) type 1 25 mv type 2 0 v oh high-level output voltage (r) i oh = ? 8 ma 2.4 v v ol low-level output voltage (r) i ol = 8 ma 0.4 v i ih high-level input current ( re) v ih = 2 v to v cc ? 10 0 a i il low-level input current ( re) v il = gnd to 0.8 v ? 10 0 a i oz high-impedance output current (r) v o = 0 v or 3.6 v ? 10 15 a c a or c b input capacitance v i = 0.4 sin(30e6 t) + 0.5 v (3) , other input at 1.2 v 3 pf c ab differential input capacitance v ab = 0.4 sin(30e6 t) v (3) 2.5 pf c a/b input capacitance balance, (c a/ c b ) 0.99 1.01 pf (1) all typical values are at 25 c and with a 3.3-v supply voltage. (2) hp4194a impedance analyzer (or equivalent) 6.8 electrical characteristics ? bus input and output over recommended operating conditions unless otherwise noted parameter test conditions min typ (1) max unit i a receiver or transceiver with driver disabled input current v a = 3.8 v, v b = 1.2 v, 0 32 a v a = 0 v or 2.4 v, v b = 1.2 v ? 20 20 v a = ? 1.4 v, v b = 1.2 v ? 32 0 i b receiver or transceiver with driver disabled input current v b = 3.8 v, v a = 1.2 v 0 32 a v b = 0 v or 2.4 v, v a = 1.2 v ? 20 20 v b = ? 1.4 v, v a = 1.2 v ? 32 0 i ab receiver or transceiver with driver disabled differential input current (i a ? i b ) v a = v b, 1.4 v a 3.8 v ? 4 4 a i a(off) receiver or transceiver power-off input current v a = 3.8 v, v b = 1.2 v, 0 v v cc 1.5 v 0 32 a v a = 0 v or 2.4 v, v b = 1.2 v, 0 v v cc 1.5 v ? 20 20 v a = ? 1.4 v, v b = 1.2 v, 0 v v cc 1.5 v ? 32 0 i b(off) receiver or transceiver power-off input current v b = 3.8 v, v a = 1.2 v, 0 v v cc 1.5 v 0 32 a v b = 0 v or 2.4 v, v a = 1.2 v, 0 v v cc 1.5 v ? 20 20 v b = ? 1.4 v, v a = 1.2 v, 0 v v cc 1.5 v ? 32 0 i ab(off) receiver input or transceiver power-off differential input current (i a ? i b ) v a = v b , 0 v v cc 1.5 v, ? 1.4 v a 3.8 v ? 4 4 a c a transceiver with driver disabled input capacitance v a = 0.4 sin (30e6 t) + 0.5 v (2) , v b = 1.2 v 5 pf c b transceiver with driver disabled input capacitance v b = 0.4 sin (30e6 t) + 0.5 v (2) , v a = 1.2 v 5 pf c ab transceiver with driver disabled differential input capacitance v ab = 0.4 sin (30e6 t)v (2) 4 pf c a/b transceiver with driver disabled input capacitance balance, (c a /c b ) 0.99 1.01 pf
7 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated (1) all typical values are at 25 c and with a 3.3-v supply voltage. (2) part-to-part skew is defined as the difference in propagation delays between two devices that operate at the same v/t conditions. (3) jitter is ensured by design and characterization. stimulus jitter has been subtracted from the numbers. (4) t r = t f = 0.5 ns (10% to 90%), measured over 30k samples. (5) peak-to-peak jitter includes jitter due to pulse skew (t sk(p) ). (6) t r = t f = 0.5 ns (10% to 90%), measured over 100k samples. 6.9 switching characteristics ? driver over recommended operating conditions unless otherwise noted parameter test conditions min typ (1) max unit t plh propagation delay time, low-to-high-level output see figure 6 2 2.5 3.5 ns t phl propagation delay time, high-to-low-level output 2 2.5 3.5 ns t r differential output signal rise time 2 ns t f differential output signal fall time 2 ns t sk(p) pulse skew (|t phl ? t plh |) 30 150 ps t sk(pp) part-to-part skew (2) 0.9 ns t jit(per) period jitter, rms (1 standard deviation) (3) 100-mhz clock input (4) 1 2 ps t jit(pp) peak-to-peak jitter (3) (5) 200 mbps 2 15 ? 1 prbs input (6) 160 210 ps t phz disable time, high-level-to-high-impedance output see figure 7 4 7 ns t plz disable time, low-level-to-high-impedance output 4 7 ns t pzh enable time, high-impedance-to-high-level output 4 7 ns t pzl enable time, high-impedance-to-low-level output 4 7 ns (1) all typical values are at 25 c and with a 3.3-v supply voltage. (2) part-to-part skew is defined as the difference in propagation delays between two devices that operate at the same v/t conditions. (3) jitter is ensured by design and characterization. stimulus jitter has been subtracted from the numbers. (4) v id = 200 mv pp (mlvd201b, 203b), v id = 400 mv pp (mlvd206b, 207b), v cm = 1 v, t r = t f = 0.5 ns (10% to 90%), measured over 30k samples. (5) peak-to-peak jitter includes jitter due to pulse skew (t sk(p) ) (6) v id = 200 mv pp (mlvd201b, 203b), v id = 400 mv pp (mlvd206b, 207b), v cm = 1 v, t r = t f = 0.5 ns (10% to 90%), measured over 100k samples. 6.10 switching characteristics ? receiver over recommended operating conditions unless otherwise noted parameter test conditions min typ (1) max unit t plh propagation delay time, low-to-high-level output c l = 15 pf, see figure 11 2 6 10 ns t phl propagation delay time, high-to-low-level output 2 6 10 ns t r output signal rise time 2.3 ns t f output signal fall time 2.3 ns t sk(p) pulse skew (|t phl ? t plh |) type 1 100 300 ps type 2 400 750 ps t sk(pp) part-to-part skew (2) 1 ns t jit(per) period jitter, rms (1 standard deviation) (3) 100-mhz clock input (4) 1 ps t jit(pp) peak-to-peak jitter (3) (5) type 1 200 mbps 2 15 ? 1 prbs input (6) 50 650 ps type 2 35 650 ps t phz disable time, high-level-to-high-impedance output see figure 12 6 10 ns t plz disable time, low-level-to-high-impedance output 6 10 ns t pzh enable time, high-impedance-to-high-level output 10 15 ns t pzl enable time, high-impedance-to-low-level output 10 15 ns
8 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated 6.11 typical characteristics t a = 25 c figure 1. differential output voltage vs supply voltage 7 parameter measurement information figure 2. driver voltage and current definitions a. all resistors are 1% tolerance. figure 3. differential output voltage test circuit v ab or v yz a/y b/z i a or i y v b or v z v a or v y v os v a + v b 2 v i d v cc v y + v z 2 or i b or i z i i copyright ? 2016, texas instruments incorporated v cc (v) v od (mv) 3 3.1 3.2 3.3 3.4 3.5 3.6 576 578 580 582 584 586 588 590 592 594 d001 v ab or v yz 49.9 3.32 k 3.32 k _ + 1 v v test <3.4 v a/yb/z d copyright ? 2016, texas instruments incorporated
9 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated parameter measurement information (continued) a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, pulse frequency = 1 mhz, duty cycle = 50 5%. b. c1, c2 and c3 include instrumentation and fixture capacitance within 2 cm of the d.u.t. and are 20%. c. r1 and r2 are metal film, surface mount, 1%, and located within 2 cm of the d.u.t. d. the measurement of v os(pp) is made on test equipment with a -3 db bandwidth of at least 1 ghz. figure 4. test circuit and definitions for the driver common-mode output voltage figure 5. driver short-circuit test circuit v test + - a/yb/z i os 0 v or v cc -1 v or 3.4 v copyright ? 2016, texas instruments incorporated v os r1 24.9 a/y c3 2.5 pf v os(pp) v os(ss) v os(ss) 1.3 v b/z a/y 0.7 v b/z d r2 24.9 c1 1 pf c2 1 pf copyright ? 2016, texas instruments incorporated
10 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated parameter measurement information (continued) a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 1 mhz, duty cycle = 50 5%. b. c1, c2, and c3 include instrumentation and fixture capacitance within 2 cm of the d.u.t. and are 20%. c. r1 is a metal film, surface mount, and 1% tolerance and located within 2 cm of the d.u.t. d. the measurement is made on test equipment with a -3 db bandwidth of at least 1 ghz. figure 6. driver test circuit, timing, and voltage definitions for the differential output signal output a/y output t plh t phl input c3 0.5 pf b/z d 0 v 0.9v v 0 v t f t r v cc v cc /2 0 v ss ss 0 v 0.1v ss ss c1 1 pf c2 1 pf v p(h) v p(l) r1 50 copyright ? 2016, texas instruments incorporated
11 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated parameter measurement information (continued) a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 1 mhz, duty cycle = 50 5%. b. c1, c2, c3, and c4 includes instrumentation and fixture capacitance within 2 cm of the d.u.t. and are 20%. c. r1 and r2 are metal film, surface mount, and 1% tolerance and located within 2 cm of the d.u.t. d. the measurement is made on test equipment with a -3 db bandwidth of at least 1 ghz. figure 7. driver enable and disable time circuit and definitions figure 8. maximum steady state output voltage a/yb/z 0 v or v cc 1.62 k , 1% v a , v b , v y or v z copyright ? 2016, texas instruments incorporated a/yb/z r1 24.9 t pzh t phz t pzl t plz v cc v cc /2 0 v ~ 0.6 v 0.1 v 0 v ~ 0.6 v 0 v 0.1 v de output with d at v cc output 0 v or v cc de output with d at 0 v c1 1 pf r2 24.9 c4 0.5 pf c2 1 pf d c3 2.5 pf copyright ? 2016, texas instruments incorporated
12 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated parameter measurement information (continued) a. all input pulses are supplied by an agilent 81250 stimulus system. b. the measurement is made on a tek tds6604 running tdsjit3 application software c. period jitter is measured using a 100 mhz 50 1% duty cycle clock input. d. peak-to-peak jitter is measured using a 200 mbps 2 15 ? 1 prbs input. figure 9. driver jitter measurement waveforms figure 10. receiver voltage and current definitions (v a + v b )/2 i o r v cm v o v id v a i a ab i b v b copyright ? 2016, texas instruments incorporated t c(n) 1/f0 0 v0 v period jitter 0 v diff peak to peak jitter 1/f0 prbs input output v a -v b or v y -v z v a -v b or v y -v z clock input ideal outputactual output v cc v cc /2 t jit(per) = t c(n) -1/f0 t jit(pp) 0 v v cc v cc /2 0 v v a -v b or v y -v z v a -v b or v y -v z copyright ? 2016, texas instruments incorporated
13 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated (1) h= high level, l = low level, output state assumes receiver is enabled ( re = l) table 1. type-1 receiver input threshold test voltages applied voltages resulting differential input voltage resulting common- mode input voltage receiver output (1) v ia v ib v id v ic 2.400 0.000 2.400 1.200 h 0.000 2.400 ? 2.400 1.200 l 3.425 3.375 0.050 3.4 h 3.375 3.425 ? 0.050 3.4 l ? 0.975 ? 1.025 0.050 ? 1 h ? 1.025 ? 0.975 ? 0.050 ? 1 l (1) h= high level, l = low level, output state assumes receiver is enabled ( re = l) table 2. type-2 receiver input threshold test voltages applied voltages resulting differential input voltage resulting common- mode input voltage receiver output (1) v ia v ib v id v ic 2.400 0.000 2.400 1.200 h 0.000 2.400 ? 2.400 1.200 l 3.475 3.325 0.150 3.4 h 3.425 3.375 0.050 3.4 l ? 0.925 ? 1.075 0.150 ? 1 h ? 0.975 ? 1.025 0.050 ? 1 l a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 1 mhz, duty cycle = 50 5%. c l is a combination of a 20%-tolerance, low-loss ceramic, surface-mount capacitor and fixture capacitance within 2 cm of the d.u.t. b. the measurement is made on test equipment with a ? 3 db bandwidth of at least 1 ghz. figure 11. receiver timing test circuit and waveforms 1.2 v 1 v t plh 0.2 v C0.2 v v a v b v id 90% v oh v ol t phl 10% t f t r v o v cc /2 v o v id v b v a c l 0 v 15 pf
14 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated a. all input pulses are supplied by a generator having the following characteristics: t r or t f 1 ns, frequency = 1 mhz, duty cycle = 50 5%. b. r l is 1% tolerance, metal film, surface mount, and located within 2 cm of the d.u.t. c. c l is the instrumentation and fixture capacitance within 2 cm of the dut and 20%. figure 12. receiver enable and disable time test circuit and waveforms 15 pf t pzl t plz v ol v ol +0.5 v v o r l 499 _ + v test ba re 1.2 v inputs v cc 1 vv cc v cc /2 0 vv cc v cc /2 v test a re r 0 v 1.4 v a t pzh t phz 0 v v oh C 0.5 v v cc v cc /2 0 vv oh v cc /2 re v o r output v test c l
15 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated a. all input pulses are supplied by an agilent 8304a stimulus system. b. the measurement is made on a tek tds6604 running tdsjit3 application software c. period jitter is measured using a 10 mhz 50 1% duty cycle clock input. d. peak-to-peak jitter is measured using a 200 mbps 2 15 -1 prbs input. figure 13. receiver jitter measurement waveforms t c(n) 1/f0 period jitter peak-to-peak jitter 1/f0 prbs input output clock input ideal output actualoutput t jit(per) = t c(n) C1/f0 t jit(pp) v a Cv b inputs v a Cv b 0.2 v C type 1 0.4 v tC ype 2 v ic 1 v v oh v cc /2 v ol v oh v ol v cc /2 v oh v ol v cc /2 v a v b
16 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated 8 detailed description 8.1 overview the sn65mlvd20xb family of devices are multipoint-low-voltage differential (m-lvds) line drivers and receivers, which are optimized to operate at signaling rates up to 200 mbps. all parts comply with the multipoint low-voltage differential signaling (m-lvds) standard tia/eia-899. these circuits are similar to their tia/eia-644 standard compliant lvds counterparts, with added features to address multipoint applications. the driver output has been designed to support multipoint buses presenting loads as low as 30 , and incorporates controlled transition times to allow for stubs off of the backbone transmission line. these devices have type-1 and type-2 receivers that detect the bus state with as little as 50 mv of differential input voltage over a common-mode voltage range of ? 1 v to 3.4 v. the type-1 receivers exhibit 25 mv of differential input voltage hysteresis to prevent output oscillations with slowly changing signals or loss of input. type-2 receivers include an offset threshold to provide a known output state under open-circuit, idle-bus, and other fault conditions. 8.2 functional block diagrams figure 14. block diagram SN65MLVD201B, sn65mlvd206b figure 15. block diagram sn65mlvd203b, sn65mlvd207b 8.3 feature description 8.3.1 power-on-reset the sn65mlvd20xb family of devices operates and meets all the specified performance requirements for supply voltages in the range of 3 v to 3.6 v. when the supply voltage drops below 1.5 v (or is turning on and has not yet reached 1.5 v), power-on reset circuitry set the driver output to a high-impedance state. 8.3.2 esd protection the bus terminals of the sn65mlvd20xb family possess on-chip esd protection against 8-kv human body model (hbm) and 8-kv iec61000-4-2 contact discharge. the iec-esd test is far more severe than the hbm- esd test. the 50% higher charge capacitance, cs, and 78% lower discharge resistance, r d of the iec model produce significantly higher discharge currents than the hbm-model. as stated in the iec 61000-4-2 standard, contact discharge is the preferred test method; although iec air-gap testing is less repeatable than contact testing, air discharge protection levels are inferred from the contact discharge test results. 54 2 3 de d re r 12 11 ab 10 9 yz copyright ? 2016, texas instruments incorporated 4 31 2 de d re r 67 ab copyright ? 2016, texas instruments incorporated
17 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated feature description (continued) figure 16. hbm and iec-esd models and currents in comparison (hbm values in parenthesis) 8.4 device functional modes 8.4.1 operation with v cc < 1.5 v bus pins will be high impedance under this condition. 8.4.2 operations with 1.5 v v cc < 3 v operation with supply voltages in the range of 1.5 v v cc < 3 v is undefined and no specific device performance is guaranteed in this range. 8.4.3 operation with 3 v v cc < 3.6 v operation with the supply voltages greater than or equal to 3 v and less than or equal to 3.6 v is normal operation. 8.4.4 device function tables (1) h = high level, l = low level, z = high impedance, x = don ' t care, ? - indeterminate table 3. type-1 receiver (201b and 203b) (1) inputs output v id = v a - v b re r v id 50 mv l h ? 50 mv < v id < 50 mv l ? v id ? 50 mv l l x h z x open z (1) h = high level, l = low level, z = high impedance, x = don ' t care, ? - indeterminate table 4. type-2 receiver (206b and 207b) (1) inputs output v id = v a - v b re r v id 150 mv l h 50 mv < v id < 150 mv l ? v id 50 mv l l x h z x open z r c r d c s highvoltage pulse generator device under test current (a) 4035 30 25 20 15 10 50 time (ns) 0 50 100 150 200 250 300 10kv iec 10kv hbm 330 (1.5 k) 150 pf (100 pf) 50 m (1 m) copyright ? 2016, texas instruments incorporated
18 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated (1) h = high level, l = low level, z = high impedance, x = don ' t care, ? - indeterminate table 5. driver (1) inputs enable outputs d de a b l h l h h h h l open h l h x open z z x l z z 8.4.5 equivalent input and output schematic diagrams 360 k 400 v cc driver input and driver enable d or de 7 v 400 v cc re 7 v receiver enable v cc 7 v 10 10 receiver output 360 k driver output a/y or b/z r v cc 200 k 250 k 200 k 250 k 100 k 100 k v cc receiver input b a copyright ? 2016, texas instruments incorporated
19 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated 9 application and implementation note information in the following applications sections is not part of the ti component specification, and ti does not warrant its accuracy or completeness. ti ? s customers are responsible for determining suitability of components for their purposes. customers should validate and test their design implementation to confirm system functionality. 9.1 application information the sn65mlvd20xb family of devices are multipoint line drivers and receivers. the functionality of these devices is simple, yet extremely flexible, leading to their use in designs ranging from wireless base stations to desktop computers. 9.2 typical application 9.2.1 multipoint communications in a multipoint configuration many transmitters and many receivers can be interconnected on a single transmission line. the key difference compared to multi-drop is the presence of two or more drivers. such a situation creates contention issues that need not be addressed with point-to-point or multidrop systems. multipoint operation allows for bidirectional, half-duplex communication over a single balanced media pair. to support the location of the various drivers throughout the transmission line, double termination of the transmission line is now necessary. the major challenge that system designers encounter are the impedance discontinuities that device loading and device connections (stubs) introduce on the common bus. matching the impedance of the loaded bus and using signal drivers with controlled signal edges are the keys to error-free signal transmissions in multipoint topologies. figure 17. multipoint configuration 9.2.2 design requirements for this design example, use the parameters listed in table 6 . table 6. design parameters parameters values driver supply voltage 3 to 3.6 v driver input voltage 0.8 to 3.3 v driver signaling rate dc to 200 mbps interconnect characteristic impedance 100 termination resistance (differential) 100 number of receiver nodes 2 to 32 receiver supply voltage 3 to 3.6 v receiver input voltage 0 to (v cc ? 0.8) v receiver signaling rate dc to 200 mbps ground shift between driver and receiver 1 v r d r d r d r d ~ 100 ~ ~ 100 ~
20 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated 9.2.3 detailed design procedure 9.2.3.1 supply voltage the sn65mlvd20xb are operated from a single supply. the devices can support operation with a supply as low as 3 v and as high as 3.6 v. 9.2.3.2 supply bypass capacitance bypass capacitors play a key role in power distribution circuitry. at low frequencies, power supply offers very low- impedance paths between its terminals. however, as higher frequency currents propagate through power traces, the source is often incapable of maintaining a low-impedance path to ground. bypass capacitors are used to address this shortcoming. usually, large bypass capacitors (10 f to 1000 f) at the board level do a good job up into the khz range. due to their size and length of their leads, large capacitors tend to have large inductance values at the switching frequencies. to solve this problem, smaller capacitors (in the nf to f range) must be installed locally next to the integrated circuit. multilayer ceramic chip or surface-mount capacitors (size 0603 or 0805) minimize lead inductances of bypass capacitors in high-speed environments, because their lead inductance is about 1 nh. for comparison purposes, a typical capacitor with leads has a lead inductance around 5 nh. the value of the bypass capacitors used locally with m-lvds chips can be determined by equation 1 and equation 2 , according to high speed digital design ? a handbook of black magic by howard johnson and martin graham (1993). a conservative rise time of 4 ns and a worst-case change in supply current of 100 ma covers the whole range of m-lvds devices offered by texas instruments. in this example, the maximum power supply noise tolerated is 100 mv; however, this figure varies depending on the noise budget available for the design. (1) (2) figure 18 shows a configuration that lowers lead inductance and covers intermediate frequencies between the board-level capacitor ( > 10 f) and the value of capacitance found above (0.004 f). place the smallest value of capacitance as close as possible to the chip. figure 18. recommended m-lvds bypass capacitor layout 9.2.3.3 driver input voltage the input stage accepts lvttl signals. the driver will operate with a decision threshold of approximately 1.4 v. 9.2.3.4 driver output voltage the driver outputs a steady state common mode voltage of 1 v with a differential signal of 540 v under nominal conditions. 0.1 f 0.004 f 3.3 v mlvds 100 ma c 4ns 0.004 f 100 mv ? ? = = m ? ? maximum step change supply current chip rise time maximum power supply noise i c t v ? ? d = ? ? d ?
21 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated 9.2.3.5 termination resistors as shown earlier, an m-lvds communication channel employs a current source driving a transmission line which is terminated with two resistive loads. these loads serve to convert the transmitted current into a voltage at the receiver input. to ensure good signal integrity, the termination resistors should be matched to the characteristic impedance of the transmission line. the designer should ensure that the termination resistors are within 10% of the nominal media characteristic impedance. if the transmission line is targeted for 100- impedance, the termination resistors should be between 90 and 110 . the line termination resistors are typically placed at the ends of the transmission line. 9.2.3.6 receiver input signal the m-lvds receivers herein comply with the m-lvds standard and correctly determine the bus state. these devices have type-1 and type-2 receivers that detect the bus state with as little as 50 mv of differential voltage over the common mode range of ? 1 v to 3.4 v. 9.2.3.7 receiver input threshold (failsafe) the mlvds standard defines a type-1 and type-2 receiver. type-1 receivers have their differential input voltage thresholds near zero volts. type-2 receivers have their differential input voltage thresholds offset from 0 v to detect the absence of a voltage difference. the impact to receiver output by the offset input can be seen in table 7 and figure 19 . table 7. receiver input voltage threshold requirements receiver type output low output high type 1 ? 2.4 v v id ? 0.05 v 0.05 v v id 2.4 v type 2 ? 2.4 v v id 0.05 v 0.15 v v id 2.4 v figure 19. expanded graph of receiver differential input voltage showing transition region 9.2.3.8 receiver output signal receiver outputs comply with lvttl output voltage standards when the supply voltage is within the range of 3 v to 3.6 v. 9.2.3.9 interconnecting media the physical communication channel between the driver and the receiver may be any balanced paired metal conductors meeting the requirements of the m-lvds standard, the key points which will be included here. this media may be a twisted pair, twinax, flat ribbon cable, or pcb traces. the nominal characteristic impedance of the interconnect should be between 100 and 120 with variation no more than 10% (90 to 132 ). -100 -50 0 50 100 150 200 type 1 transition regions type 2 low high low high differential input voltage (mv)
22 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated 9.2.3.10 pcb transmission lines as per snla187 , figure 20 depicts several transmission line structures commonly used in printed-circuit boards (pcbs). each structure consists of a signal line and a return path with uniform cross-section along its length. a microstrip is a signal trace on the top (or bottom) layer, separated by a dielectric layer from its return path in a ground or power plane. a stripline is a signal trace in the inner layer, with a dielectric layer in between a ground plane above and below the signal trace. the dimensions of the structure along with the dielectric material properties determine the characteristic impedance of the transmission line (also called controlled-impedance transmission line). when two signal lines are placed close by, they form a pair of coupled transmission lines. figure 20 shows examples of edge-coupled microstrips, and edge-coupled or broad-side-coupled striplines. when excited by differential signals, the coupled transmission line is referred to as a differential pair. the characteristic impedance of each line is called odd-mode impedance. the sum of the odd-mode impedances of each line is the differential impedance of the differential pair. in addition to the trace dimensions and dielectric material properties, the spacing between the two traces determines the mutual coupling and impacts the differential impedance. when the two lines are immediately adjacent; for example, if s is less than 2 w, the differential pair is called a tightly- coupled differential pair. to maintain constant differential impedance along the length, it is important to keep the trace width and spacing uniform along the length, as well as maintain good symmetry between the two lines. figure 20. controlled-impedance transmission lines 0 r 87 5.98 h z ln 0.8 w t 1.41 ? h ? 1 > @ > @ 0 r 1.9 2 h t 60 z ln 0.8 w t ? ? h ? 1 s 0.96 h diff 0 z 2 z 1 0.48 e u ? u u u ? ? 1 s 2.9 h diff 0 z 2 z 1 0.347 e u ? u u u ? ? 1 co-planar coupled microstrips broad-side coupled striplines edge-coupled edge-coupled single-ended microstrip single-ended stripline w h t w t h h s h differential microstrip differential stripline s h s h h g g w w w s
23 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated 9.2.4 application curves v cc = 3.3 v t a = 25 c v cc = 3.3 v t a = 25 c figure 21. driver fall time figure 22. driver rise time
24 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated 10 power supply recommendations the m-lvds driver and receivers in this data sheet are designed to operate from a single power supply. both drivers and receivers operate with supply voltages in the range of 3 v to 3.6 v. in a typical application, a driver and a receiver may be on separate boards, or even separate equipment. in these cases, separate supplies would be used at each location. the expected ground potential difference between the driver power supply and the receiver power supply would be less than 1 v. board level and local device level bypass capacitance should be used and are covered supply bypass capacitance. (1) howard johnson & martin graham.1993. high speed digital design ? a handbook of black magic. prentice hall prt. isbn number 013395724. (2) mark i. montrose. 1996. printed circuit board design techniques for emc compliance. ieee press. isbn number 0780311310. (3) clyde f. coombs, jr. ed, printed circuits handbook, mcgraw hill, isbn number 0070127549. 11 layout 11.1 layout guidelines 11.1.1 microstrip vs. stripline topologies as per slld009 , printed-circuit boards usually offer designers two transmission line options: microstrip and stripline. microstrips are traces on the outer layer of a pcb, as shown in figure 23 . figure 23. microstrip topology on the other hand, striplines are traces between two ground planes. striplines are less prone to emissions and susceptibility problems because the reference planes effectively shield the embedded traces. however, from the standpoint of high-speed transmission, juxtaposing two planes creates additional capacitance. ti recommends routing m-lvds signals on microstrip transmission lines if possible. the pcb traces allow designers to specify the necessary tolerances for z o based on the overall noise budget and reflection allowances. footnotes 1 (1) , 2 (2) , and 3 (3) provide formulas for z o and t pd for differential and single-ended traces. (1) (2) (3) figure 24. stripline topology
25 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated layout guidelines (continued) 11.1.2 dielectric type and board construction the speeds at which signals travel across the board dictates the choice of dielectric. fr-4, or equivalent, usually provides adequate performance for use with m-lvds signals. if rise or fall times of ttl/cmos signals are less than 500 ps, empirical results indicate that a material with a dielectric constant near 3.4, such as rogers ? 4350 or nelco n4000-13 is better suited. once the designer chooses the dielectric, there are several parameters pertaining to the board construction that can affect performance. the following set of guidelines were developed experimentally through several designs involving m-lvds devices: ? copper weight: 15 g or 1/2 oz start, plated to 30 g or 1 oz ? all exposed circuitry should be solder-plated (60/40) to 7.62 m or 0.0003 in (minimum). ? copper plating should be 25.4 m or 0.001 in (minimum) in plated-through-holes. ? solder mask over bare copper with solder hot-air leveling 11.1.3 recommended stack layout following the choice of dielectrics and design specifications, you must decide how many levels to use in the stack. to reduce the ttl/cmos to m-lvds crosstalk, it is a good practice to have at least two separate signal planes as shown in figure 25 . figure 25. four-layer pcb board note the separation between layers 2 and 3 should be 127 m (0.005 in). by keeping the power and ground planes tightly coupled, the increased capacitance acts as a bypass for transients. one of the most common stack configurations is the six-layer board, as shown in figure 26 . figure 26. six-layer pcb board in this particular configuration, it is possible to isolate each signal layer from the power plane by at least one ground plane. the result is improved signal integrity; however, fabrication is more expensive. using the 6-layer board is preferable, because it offers the layout designer more flexibility in varying the distance between signal layers and referenced planes, in addition to ensuring reference to a ground plane for signal layers 1 and 6. 11.1.4 separation between traces the separation between traces depends on several factors; however, the amount of coupling that can be tolerated usually dictates the actual separation. low noise coupling requires close coupling between the differential pair of an m-lvds link to benefit from the electromagnetic field cancellation. the traces should be 100- ? differential and thus coupled in the manner that best fits this requirement. in addition, differential pairs should have the same electrical length to ensure that they are balanced, thus minimizing problems with skew and signal reflection. layer 4: routed plane (ttl signals) layer 3: power plane layer 2: ground plane layer 1: routed plane (mlvds signals) layer 4: ground plane layer 5: ground plane layer 4: routed plane (ttl/cmos signals) layer 3: power plane layer 2: ground plane layer 1: routed plane (mlvds signals)
26 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated layout guidelines (continued) in the case of two adjacent single-ended traces, one should use the 3-w rule, which stipulates that the distance between two traces must be greater than two times the width of a single trace, or three times its width measured from trace center to trace center. this increased separation effectively reduces the potential for crosstalk. the same rule should be applied to the separation between adjacent m-lvds differential pairs, whether the traces are edge-coupled or broad-side-coupled. figure 27. 3-w rule for single-ended and differential traces (top view) you should exercise caution when using autorouters, because they do not always account for all factors affecting crosstalk and signal reflection. for instance, it is best to avoid sharp 90 turns to prevent discontinuities in the signal path. using successive 45 turns tends to minimize reflections. 11.1.5 crosstalk and ground bounce minimization to reduce crosstalk, it is important to provide a return path to high-frequency currents that is as close as possible to its originating trace. a ground plane usually achieves this. because the returning currents always choose the path of lowest inductance, they are most likely to return directly under the original trace, thus minimizing crosstalk. lowering the area of the current loop lowers the potential for crosstalk. traces kept as short as possible with an uninterrupted ground plane running beneath them emit the minimum amount of electromagnetic field strength. discontinuities in the ground plane increase the return path inductance and should be avoided. 11.1.6 decoupling each power or ground lead of a high-speed device should be connected to the pcb through a low inductance path. for best results, one or more vias are used to connect a power or ground pin to the nearby plane. ideally, via placement is immediately adjacent to the pin to avoid adding trace inductance. placing a power plane closer to the top of the board reduces the effective via length and its associated inductance. figure 28. low inductance, high-capacitance power connection board thickness approximately 100 mil 2 mil typical 12-layer pcb 4 mil 4 mil 6 mil 6 mil v cc via gnd via top signal layer + gnd fill v dd 1 plane gnd plane signal layer buried capacitor > signal layer gnd plane v dd 2 plane bottom signal layer + gnd fill buried capacitor > gnd plane signal layers v cc plane t 2 w w ww minimum spacing as defined by pcb vendor mlvds pair ttl/cmos trace differential traces single-ended traces s =
27 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated layout guidelines (continued) bypass capacitors should be placed close to v dd pins. they can be placed conveniently near the corners or underneath the package to minimize the loop area. this extends the useful frequency range of the added capacitance. small-physical-size capacitors, such as 0402, 0201, or x7r surface-mount capacitors should be used to minimize body inductance of capacitors. each bypass capacitor is connected to the power and ground plane through vias tangent to the pads of the capacitor as shown in figure 29 (a). an x7r surface-mount capacitor of size 0402 has about 0.5 nh of body inductance. at frequencies above 30 mhz or so, x7r capacitors behave as low-impedance inductors. to extend the operating frequency range to a few hundred mhz, an array of different capacitor values like 100 pf, 1 nf, 0.03 f, and 0.1 f are commonly used in parallel. the most effective bypass capacitor can be built using sandwiched layers of power and ground at a separation of 2 to 3 mils. with a 2-mil fr4 dielectric, there is approximately 500 pf per square inch of pcb. many high-speed devices provide a low-inductance gnd connection on the backside of the package. this center pad must be connected to a ground plane through an array of vias. the via array reduces the effective inductance to ground and enhances the thermal performance of the small surface mount technology (smt) package. placing vias around the perimeter of the pad connection ensures proper heat spreading and the lowest possible die temperature. placing high-performance devices on opposing sides of the pcb using two gnd planes (as shown in figure 20 ) creates multiple paths for heat transfer. often thermal pcb issues are the result of one device adding heat to another, resulting in a very high local temperature. multiple paths for heat transfer minimize this possibility. in many cases the gnd pad makes the optimal decoupling layout impossible to achieve due to insufficient pad-to-pad spacing as shown in figure 29 (b). when this occurs, placing the decoupling capacitor on the backside of the board keeps the extra inductance to a minimum. it is important to place the v dd via as close to the device pin as possible while still allowing for sufficient solder mask coverage. if the via is left open, solder may flow from the pad and into the via barrel. this will result in a poor solder connection. (a) (b) figure 29. typical decoupling capacitor layouts 11.2 layout example at least two or three times the width of an individual trace should separate single-ended traces and differential pairs to minimize the potential for crosstalk. single-ended traces that run in parallel for less than the wavelength of the rise or fall times usually have negligible crosstalk. increase the spacing between signal paths for long parallel runs to reduce crosstalk. boards with limited real estate can benefit from the staggered trace layout, as shown in figure 30 . figure 30. staggered trace layout layer 6 layer 1 0402 v dd in in+ 0402
28 sn65mlvd206b sllsex9 ? december 2016 www.ti.com product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated layout example (continued) this configuration lays out alternating signal traces on different layers; thus, the horizontal separation between traces can be less than 2 or 3 times the width of individual traces. to ensure continuity in the ground signal path, ti recommends having an adjacent ground via for every signal via, as shown in figure 31 . note that vias create additional capacitance. for example, a typical via has a lumped capacitance effect of 1/2 pf to 1 pf in fr4. figure 31. ground via location (side view) short and low-impedance connection of the device ground pins to the pcb ground plane reduces ground bounce. holes and cutouts in the ground planes can adversely affect current return paths if they create discontinuities that increase returning current loop areas. to minimize emi problems, ti recommends avoiding discontinuities below a trace (for example, holes, slits, and so on) and keeping traces as short as possible. zoning the board wisely by placing all similar functions in the same area, as opposed to mixing them together, helps reduce susceptibility issues. signal trace uninterrupted ground plane signal trace uninterrupted ground plane signal via ground via
29 sn65mlvd206b www.ti.com sllsex9 ? december 2016 product folder links: sn65mlvd206b submit documentation feedback copyright ? 2016, texas instruments incorporated 12 device and documentation support 12.1 documentation support 12.2 receiving notification of documentation updates to receive notification of documentation updates, navigate to the device product folder on ti.com. in the upper right corner, click on alert me to register and receive a weekly digest of any product information that has changed. for change details, review the revision history included in any revised document. 12.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. design support ti's design support quickly find helpful e2e forums along with design support tools and contact information for technical support. 12.4 trademarks e2e is a trademark of texas instruments. rogers is a trademark of rogers corporation. all other trademarks are the property of their respective owners. 12.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 12.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 13 mechanical, packaging, and orderable information the following pages include mechanical, packaging, and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation.
package option addendum www.ti.com 23-dec-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples sn65mlvd206bd active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mf206b sn65mlvd206bdr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 mf206b (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 23-dec-2016 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant sn65mlvd206bdr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 package materials information www.ti.com 22-dec-2016 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) sn65mlvd206bdr soic d 8 2500 340.5 338.1 20.6 package materials information www.ti.com 22-dec-2016 pack materials-page 2

important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per jesd46, latest issue, and to discontinue any product or service per jesd48, latest issue. buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all semiconductor products (also referred to herein as ? components ? ) are sold subject to ti ? s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in ti ? s terms and conditions of sale of semiconductor products. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. ti assumes no liability for applications assistance or the design of buyers ? products. buyers are responsible for their products and applications using ti components. to minimize the risks associated with buyers ? products and applications, buyers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which ti components or services are used. information published by ti regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of significant portions of ti information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. ti is not responsible or liable for such altered documentation. information of third parties may be subject to additional restrictions. resale of ti components or services with statements different from or beyond the parameters stated by ti for that component or service voids all express and any implied warranties for the associated ti component or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of ti components in its applications, notwithstanding any applications-related information or support that may be provided by ti. buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. buyer will fully indemnify ti and its representatives against any damages arising out of the use of any ti components in safety-critical applications. in some cases, ti components may be promoted specifically to facilitate safety-related applications. with such components, ti ? s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. nonetheless, such components are subject to these terms. no ti components are authorized for use in fda class iii (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. only those ti components which ti has specifically designated as military grade or ? enhanced plastic ? are designed and intended for use in military/aerospace applications or environments. buyer acknowledges and agrees that any military or aerospace use of ti components which have not been so designated is solely at the buyer ' s risk, and that buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. ti has specifically designated certain components as meeting iso/ts16949 requirements, mainly for automotive use. in any case of use of non-designated products, ti will not be responsible for any failure to meet iso/ts16949. products applications audio www.ti.com/audio automotive and transportation www.ti.com/automotive amplifiers amplifier.ti.com communications and telecom www.ti.com/communications data converters dataconverter.ti.com computers and peripherals www.ti.com/computers dlp ? products www.dlp.com consumer electronics www.ti.com/consumer-apps dsp dsp.ti.com energy and lighting www.ti.com/energy clocks and timers www.ti.com/clocks industrial www.ti.com/industrial interface interface.ti.com medical www.ti.com/medical logic logic.ti.com security www.ti.com/security power mgmt power.ti.com space, avionics and defense www.ti.com/space-avionics-defense microcontrollers microcontroller.ti.com video and imaging www.ti.com/video rfid www.ti-rfid.com omap applications processors www.ti.com/omap ti e2e community e2e.ti.com wireless connectivity www.ti.com/wirelessconnectivity mailing address: texas instruments, post office box 655303, dallas, texas 75265 copyright ? 2016, texas instruments incorporated

▲Up To Search▲

Price & Availability of SN65MLVD201B

	To Download SN65MLVD201B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .